FAR=Val_0x0
FIFO Access Register
| FAR | This bit is used to enable a FIFO access mode for testing, so that the Rx FIFO can be written and the Tx FIFO can be read when FIFOs are enabled. When FIFOs are not enabled it allows the UART_RBR[RBR] to be written by the master and the UART_THR[THR] to be read by the master. Note: When the FIFO access mode is enabled/disabled, the control portion of the Rx FIFO and Tx FIFO is reset and the FIFOs are treated as empty. 0 (Val_0x0): FIFO access mode disabled 1 (Val_0x1): FIFO access mode enabled |